Faculty

Dr. Binsu J Kailath

Associate Professor

E-mail: bkailath@iiitdm.ac.in | Ph: +91-44-27476341 | Room No: 108 E

Education

IIT Madras

Chennai

PhD in Ultra Thin Oxide MOS Devices, Dept. of Electrical Engineering

2003 - 2007

IIT Madras

Chennai

M.Tech. in MicroElectronics and VLSI Design, Dept. of Electrical Engineering

1999 - 2001

University of Calicut

Kerala

B.Tech. in Electronics and Communication Engineering

1988 - 1992

Specialization

  1. Micro Electronics and VLSI Design

Research Interests

  1. Mixed Signal IC Design

  2. Neuromorphic Circuits

  3. Microelectronics and MEMS

Honours + Awards + Recognitions

  1. Lower Secondary School Scholarship (1980)

  2. Upper Secondary School Scholarship (1983)

  3. National Merit Scholarship (1986)

  4. President's Guide Award from the President of India (1986)

  5. DAAD fellowship for post-doctoral research, 2011

  6. Best Paper Award in INDICON 2015 held in New Delhi in Dec. 2015

  7. Industry Ready Technology award in the '' IEEE TECHSYM 2016, IIT Kharagpur, 27/09/16 - 02/10/16

  8. Reviewer for IEEE Transactions on Circuits And Systems II (TCAS II)

  9. Reviewer for Microelectronics Journal by Elsevier

  10. Reviewer for Materials Science and Engineering B Journal by Elsevier

  11. Member, Board of Studies, IIITDM Kurnool

Work Experience

Teaching

  1. Faculty Member in Electronics Engineering in College of Engineering, Chengannur, Kerala, for 8 years

  2. Faculty Member in Electronics Engineering in IIITDM Kancheepuram from Oct 2008

Research

  1. Switch Capacitor circuit simulator Development (ongoing)

  2. Sigma Delta ADC (ongoing, fabrication is planned in SCL, Punjab under SMDP-C2SD sponsored

  3. by MeitY))

  4. Composite PFD based PLL (design is completed and fabrication is planned in SCL, Punjab under SMDP-C2SD sponsored by MeitY)

  5. Fabrication, characterization and extraction of conduction Mechanisms in SiC MIS Capacitors with High-k dielectrics of which fabrication and characterization was carried out in Centre for Nano Science and Engg, IISc Bangalore through INUP (completed)

  6. In the sponsored project ???Novel Oxidation Techniques for improvement in the Electrical properties of Ultra-thin SiO2 for VLSI technology??? coordinated by Prof. Nandita DasGupta in Microelectronics and MEMS Laboratory, Dept. of Electrical Engineering, IIT Madras (completed)

  7. Study of Novel gate oxidation techniques for future MOS devices (completed)

  8. Study of high-k gate dielectrics for future MOS devices (completed)

  9. Study of Laser Induced Oxidation as a viable technique to grow ultra thin SiO2 (completed)

  10. Study of Rapid thermal Oxidation technique to grow ultra thin SiO2 (completed)

  11. Optimization of HNO3 Vapour oxidation technique to grow ultra thin SiO2 (completed)

  12. Study of the effect of phosphorus doping on passivation of grain boundaries in poly Si TFTs (completed)

Professional Membership

  1. Member, IEEE

  2. Life Member, ISTE

Professional Service

  1. Member, Board of Studies, IIITDM Kurnool

  2. CURRICULUM DEVELOPMENT

  3. B Tech programme:

  4. Electronics Engg Design and Manufacturing curriculum adopted for 2008 to 2013 batches admissions

  5. Electronics and Communication Engineering Design and Manufacturing curriculum adopted from 2014 batch admissions

  6. Dual degree programme:

  7. B Tech in Electronics and Communication Engg Design and Manufacturing and M Tech in VLSI and Electronic System Design from 2014 batch admissions

  8. M Des programme:

  9. Electronic Systems adopted for admissions from 2010 - 2016

  10. STREAM COORDINTAOR

  11. Electronics Engineering (2008-2013)

  12. M DES AND PHD ADMISSION COORDINATOR (2009 - 2014)

  13. DESIGNERS??? CLUB COORDINATOR (2011 - 2014)

  14. CHAIRPERSON, DISCIPLINARY COMMITTEE (2012- 2014)

  15. WOMEN???S FORUM COORDINATOR (2009 - 2015)

  16. GUIDANCE AND COUNSELING (2011 - 2015)

Teaching

  1. ELE 101, ELE 103T Basic Electrical and Electronics Engg (2008, 2014, 2015, 2016)

  2. ELE 106 Digital Logic Design (2011, 2012)

  3. ELE 203 Control Systems (2009)

  4. ELE 206 Networks and Systems (2009, 2010)

  5. ELE 213, ELE 223T Analog Circuits (2009, 2010, 2011, 2012, 2013, 2014, 2015, 2018)

  6. ELE 306 Analog IC Applications (2010, 2011, 2012)

  7. ELE 501 Design and Applications of Analog ICs (2011, 2012, 2013)

  8. MEMS (2012, 2014)

  9. ELE 302T Electronic Manufacturing and Prototyping (2016)

  10. ELE 311 VLSI Design (2015, 2016)

  11. ELE 318T Digtal IC Design (2017, 2019)

  12. ELE 522T Analog IC Design (2017, 2018, 2019)

  13. ELE 411T Digital Systems Engineering (2018, 2019)

Books

  1. Book Chapter

  2. Binsu J Kailath, Abdul Majeed K. K., ???Composite PFD based Low Power Low Noise Fast Lock-in PLL,??? in VLSI and Post-CMOS Devices, Circuits and Modelling, IET, 2019, under print.

Journal Publications

  1. International Refereed Journals

  2. E. Papanasam, Binsu J Kailath (2019) “Extraction and Analysis of Gate Leakage Current Mechanism in Silicon Carbide (SiC) MIS Capacitors", Accepted for Publication in IETE Journal of Research

  3. Manne SaiSravan, SudhaNatarajan, Eswar SaiKrishna, Binsu JKailath (2018) “Fast and accurate on-road vehicle detection based on color intensity segregation”, Procedia Computer Science, Vol. 133, pp 594-603

  4. E. Papanasam, Binsu J Kailath (2018),”Effect of Post Deposition Annealing and Post Metallization Annealing on Electrical and Structural Characteristics of Pd/Al2O3/6H-SiC MIS Capacitors”, Microelectronics International, Vol. 35, Issue 2, pp 65-73.

  5. Abdul Majeed and Binsu Kailath (2018), “Novel PLL Architecture with a Composite PFD and variable Loop Filter” IET Circuits, Devices & Systems, Volume: 12 , Issue: 3 , 5 pp 256 - 262

  6. Abdul Majeed, K.K. Kailath, B.J. (2017) "Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP", Analog Integrated Circuits and Signal Processing, Vol. 93, number 1, pp 29-39

  7. E.Papanasam and Binsu J Kailath (2017), “Improvement on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors using post deposition annealing and post metallization annealing” Applied Surface Science, 413, 66–71.

  8. E. Papanasam, Binsu J Kailath (2016): ”Effect of Post Deposition Annealing and Post Metallization Annealing on Electrical and Structural Characteristics of Pd/Al2O3/6H-SiC MIS Capacitors”, Accepted for Publication in Microelectronics International Journal

  9. Abdul Majeed K. K., and Binsu J. Kailath (2016): “Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur,” IEICE Electronics Express, Volume 13, number 10, page: 20160328

  10. Abdul Majeed K K and Binsu J Kailath (2013): “A Novel Phase Frequency Detector for a High Frequency PLL Design”, Procedia Engineering 64, 377 – 384

  11. Binsu J KailathDasGupta, A., DasGupta, N., B N Singh and L M Kukreja (2009): Growth of ultra-thin SiO2 by laser-induced oxidation. Semiconductor Science and Technology 24, 105011

  12. Binsu J KailathDasGupta, A. and DasGupta, N. (2009): Ultra Thin Oxide by Chemical Vapour Oxidation of Si. Transactions of Electro Chemical Society22, 1, 151-159.

  13. Binsu J KailathDasGupta, N. and DasGupta, A. (2007): Optimization of ac anodization parameters for the improvement of electrical properties of thermally grown ultrathin gate oxide. Solid State Electronics 51, 762-770.

  14. Binsu J KailathDasGupta, N. and DasGupta, A. (2007): Electrical and Reliability Characteristics of MOS Devices with ultrathin SiO2 grown in nitric acid solutions. IEEE Transactions on Device and Material Reliability 7, 602-610.

  15. Binsu J KailathDasGupta, N. and DasGupta, A. (2007): Improved Electrical Characteristics of MOS devices with gate oxide grown by chemical oxidation. Transactions of Electro Chemical Society 8, 105-110.

  16. Binsu J KailathDasGupta, N. and DasGupta, A. (2006): Improved Electrical Characteristics by anodic oxidation with superimposed dc and ac voltages. IETE Journal of Research 5, 357-363

Conference Publications

  1. Amrutha Manoharan, Gadamsetty Muralidhar, Binsu J Kailath, ’A Novel Method to Implement STDP Learning Rule in Verilog’, IEEE Region 10 Symposium (TENSYMP), 5-7 June 2020, Dhaka, Bangladesh.

  2. Nithya K, Muralidhar Gadamsetty and Binsu J Kailath, “FPGA Implementation of Speech Recognizer for Isolated Words”, accepted for Lecture presentation at 2019 IEEE 5th International Symposium on Smart Electronic Systems (iSES), to be held in Rourkela, India from December 16-18, 2019.

  3. Muralidhar Gadamsetty and Binsu J Kailath, “The Simplest and Efficient Form of Spiking Neuron", accepted for Lecture presentation at 2019 IEEE Asia Pacific Conference on Circuits and Systems, to be held in Bangkok, Thailand from November 11-14, 2019.

  4. Manne Sai Sravan, Sudha Natarajan, Eswar Sai Krishna, Binsu J Kailath (2018) “Fast and accurate on-road vehicle detection based on color intensity segregation” “International Conference on Robotics and Smart Manufacturing (RoSMa2018), 19 – 21 July 2018, Chennai

  5. Monisha Yuvaraj, Nandita Bhaskhar and Binsu J Kailath (2017) "Design of an Optimized MAC Unit using Integrated Vedic Multiplier", Accepted for ICMDCS, to be held in VIT Vellore, from 10th - 12th August 2017

  6. Vani Mrudula Magapati and Binsu J Kailath (2017) "Switched Capacitor Circuit Simulator for Noise Analysis Using Adjoint Network Approach" Accepted for ICMDCS, to be held in VIT Vellore, from 10th - 12th August 2017

  7. Dheepika K, Jevashankari S, Vippin Chandhar and Binsu J Kailath (2017): "Realization of Multiplier using Delay Efficient Cyclic Redundant Adder" Accepted for VDAT 2017 to be held in IIT Roorkee from 28th June to 2nd July, 2017

  8. Binsu J. Kailath, G. Dinesh, “QSCsim — Charge Based Switched Capacitor Simulator”, Special Session in 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 19-21 Dec. 2016, Page: 284

  9. E.Papanasam, Binsu J Kailath, "Effect of Post Metallization Annealing on the Electrical Characteristics of Pd/HfO2/6H-SiC MIS Capacitors and Extraction of Conduction Mechanisms," IEEE 3rd International Conference on Emerging Electronics (ICEE), Dec 2016, IIT Bombay

  10. Majeed K. K. and Binsu J. Kailath, “Analysis and Design of Low Power Nonlinear PFD architectures for a Fast Locking PLL,'' IEEE TECHSYM 2016, IIT Kharagpur, 27th Sep 2nd Oct 2016 (Won the Industry Ready Technology Award)

  11. Sriramprasath, Sudha Natarajan and Binsu J Kailath, “Accelerating Occupancy Grid Map Computation with GPU for Real-Time Obstacle Detection, 22ndannual International Conference on Advanced Computing and Communications (ADCOM 2016) at Bangalore during 8th -10th September 2016.

  12. Karthikeyan Saravanan, G.Dinesh and Binsu J Kailath, “Improved Alias Rejection Using Interleaved CIC Decimation Filter,” presented in IEEE 14th International NEWCAS Conference in Vancouver, Canada, June 26-29, 2016.

  13. Muralidhar Gadamsetty, G.Dinesh and Binsu J Kailath, "Switched Capacitor Circuit Simulator in Q-V Domain including Non Idealities“, presented in 20th VLSI Design and Test Symposium (VDAT-2016), IIT Guwahati, May 24-27, 2016.

  14. Abdul Majeed K K and Binsu J Kailath, "CMOS Current Starved Voltage Controlled Oscillator Circuit for a Fast Locking PLL" (2015) in the 12th IEEE India International Conference, INDICON 2015, held in New Delhi from 17th to 20th Dec 2015 (Won Best Paper Award)

  15. Abhay Kumar and Binsu J Kailath, “Design of 3stage high frequency CMOS voltage controlled oscillator”, IEEE EDSSC 2015, IEEE International Conference on Electron Devices and Solid-State Circuits held from 1stto 4th June, 2015 in NTU, Singapore

  16. E.Papanasam, Binsu J Kailath, “Realization of silicon carbide MIS capacitors with high-K and high-K stack dielectric,” IEEE 12th International conference on solid state and integrated circuit technology (ICSICT)2014, Guilin, China

  17. Abdul Majeed K K and Binsu J Kailath, “A Novel Phase Frequency Detector for a High Frequency PLL Design” (2013)International Conference on Design and Manufacturing, IConDM 2013at Indian Institute of Information Technology Design and Manufacturing (IIITD&M) Kancheepuram, Chennai, India-600127 held from 18th- 20th July 2013

  18. Abdul Majeed K.K. and Binsu J Kailath, “Low power, High Frequency, Free Dead Zone PFD for a PLL Design, (2013)IEEE Faible Tension FaibleConsommation (Low Voltage Low Power) Conference held in Paris, France from 20th – 21st June 2013

  19. S. Deepak and Binsu J Kailath, Optimized MAC unit design, (2012)IEEE EDSSC 2012, IEEE International Conference on Electron Devices and Solid-State Circuits held from December 3-5, 2012 in Bangkok, Thailand

  20. HarikrishnanGopalakrishnan, Binsu J Kailath, (2012) “MIM Capacitors with stacked dielectrics” Presented in the International Conference “Tech Connect world 2012” held from 18th to 21st June 2012 in Santa Clara, USA

  21. Kalaiselvi, K., Binsu J KailathDasGupta, A., and DasGupta, N. (2009): Ultra thin gate oxide by RTO followed by Anodization, in the Proceedings of the 15th International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, December 2009.

  22. Binsu J KailathDasGupta, N. and DasGupta, A. (2009) Ultra Thin Oxide by Chemical Vapour Oxidation of Si,ECI International Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors, Xian, China, July-August 2009

  23. Binsu J Kailath,DasGupta, N., DasGupta, A., Bhattacharya, S., Armstrong, B.M., Gamble H.S., and McCarthy, J. (2007): Novel low temperature techniques for growth of ultrathin oxides for Strained Si MOS Devices. Proceedings of the 19th IEEE International Conference on Microelectronics (ICM), Cairo, Egypt, December 2007, 429-432.

  24. Binsu J Kailath Bhattacharya, S., DasGupta, A., DasGupta, N., McNeill, D.W. and Gamble, H. (2007): Effect of Nitridation on Al/HfO2/Ge MIS Capacitors. Proceedings of the 14th International Workshop on Physics of Semiconductor Devices (IWPSD), Bombay, India, December 2007, 194-197.

  25. Binsu J KailathDasGupta, N. and DasGupta, A. (2007) Improved Electrical Characteristics of MOS devices with gate oxide grown by chemical oxidation. ECI International Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors, Barga, Italy, July-August 2007.

  26. Binsu J KailathDasGupta, N. and DasGupta, A. (2006): Improved Reliability Characteristics for thermally grown ultrathin gate oxide by optimized anodic oxidation. Proceedings of the International Conference on Reliability and Safety Engineering, Chennai, India, December 2006, 508-514.

  27. Binsu J KailathMarathe, V.G., DasGupta, N. and DasGupta, A. (2005): Studies on Chemical oxidation of Silicon with Nitric Acid. Proceedings of the 13th International Workshop on Physics of Semiconductor Devices (IWPSD), New Delhi, India, December 2005, 701-704.

  28. Binsu J KailathDasGupta, N., DasGupta, A., Bhattacharya, S., Armstrong, B.M., Gamble H.S., Misra, Pankaj and Kukreja, L.M. (2005): Electrical Characterisation of Al/SiO2-TiO2/Strained Si/Relaxed SiGe MTOS Capacitors. International Conference on MEMS and Nanotechnology, Kharagpur, India, December 2005.

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